Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
Nektar
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Requirements
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Giacomo Castiglioni
Nektar
Commits
32cdb182
Commit
32cdb182
authored
10 years ago
by
Dave Moxey
Browse files
Options
Downloads
Patches
Plain Diff
Fix periodic boundary conditions when using --shared-filesystem
parent
6e3d43e2
No related branches found
Branches containing commit
No related tags found
Tags containing commit
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
library/LibUtilities/BasicUtils/SessionReader.cpp
+102
-1
102 additions, 1 deletion
library/LibUtilities/BasicUtils/SessionReader.cpp
with
102 additions
and
1 deletion
library/LibUtilities/BasicUtils/SessionReader.cpp
+
102
−
1
View file @
32cdb182
...
...
@@ -1421,7 +1421,11 @@ namespace Nektar
SessionReaderSharedPtr
vSession
=
GetSharedThisPtr
();
if
(
DefinesCmdLineArgument
(
"shared-filesystem"
))
{
if
(
GetComm
()
->
GetRank
()
==
0
)
CommSharedPtr
vComm
=
GetComm
();
vector
<
unsigned
int
>
keys
,
vals
;
int
i
;
if
(
vComm
->
GetRank
()
==
0
)
{
m_xmlDoc
=
MergeDoc
(
m_filenames
);
...
...
@@ -1433,11 +1437,108 @@ namespace Nektar
vPartitioner
->
GetCompositeOrdering
(
m_compOrder
);
vPartitioner
->
GetBndRegionOrdering
(
m_bndRegOrder
);
// Communicate orderings to the other processors.
// First send sizes of the orderings and boundary
// regions to allocate storage on the remote end.
keys
.
resize
(
2
);
keys
[
0
]
=
m_compOrder
.
size
();
keys
[
1
]
=
m_bndRegOrder
.
size
();
for
(
i
=
1
;
i
<
vComm
->
GetSize
();
++
i
)
{
vComm
->
Send
(
i
,
keys
);
}
// Construct the keys and sizes of values for composite
// ordering
CompositeOrdering
::
iterator
cIt
;
keys
.
resize
(
m_compOrder
.
size
());
vals
.
resize
(
m_compOrder
.
size
());
for
(
cIt
=
m_compOrder
.
begin
(),
i
=
0
;
cIt
!=
m_compOrder
.
end
();
++
cIt
,
++
i
)
{
keys
[
i
]
=
cIt
->
first
;
vals
[
i
]
=
cIt
->
second
.
size
();
}
// Send across data.
for
(
i
=
1
;
i
<
vComm
->
GetSize
();
++
i
)
{
vComm
->
Send
(
i
,
keys
);
vComm
->
Send
(
i
,
vals
);
for
(
cIt
=
m_compOrder
.
begin
();
cIt
!=
m_compOrder
.
end
();
++
cIt
)
{
vComm
->
Send
(
i
,
cIt
->
second
);
}
}
// Construct the keys and sizes of values for composite
// ordering
BndRegionOrdering
::
iterator
bIt
;
keys
.
resize
(
m_bndRegOrder
.
size
());
vals
.
resize
(
m_bndRegOrder
.
size
());
for
(
bIt
=
m_bndRegOrder
.
begin
(),
i
=
0
;
bIt
!=
m_bndRegOrder
.
end
();
++
bIt
,
++
i
)
{
keys
[
i
]
=
bIt
->
first
;
vals
[
i
]
=
bIt
->
second
.
size
();
}
// Send across data.
for
(
i
=
1
;
i
<
vComm
->
GetSize
();
++
i
)
{
vComm
->
Send
(
i
,
keys
);
vComm
->
Send
(
i
,
vals
);
for
(
bIt
=
m_bndRegOrder
.
begin
();
bIt
!=
m_bndRegOrder
.
end
();
++
bIt
)
{
vComm
->
Send
(
i
,
bIt
->
second
);
}
}
if
(
DefinesCmdLineArgument
(
"part-info"
))
{
vPartitioner
->
PrintPartInfo
(
std
::
cout
);
}
}
else
{
keys
.
resize
(
2
);
vComm
->
Recv
(
0
,
keys
);
int
cmpSize
=
keys
[
0
];
int
bndSize
=
keys
[
1
];
keys
.
resize
(
cmpSize
);
vals
.
resize
(
cmpSize
);
vComm
->
Recv
(
0
,
keys
);
vComm
->
Recv
(
0
,
vals
);
for
(
int
i
=
0
;
i
<
keys
.
size
();
++
i
)
{
vector
<
unsigned
int
>
tmp
(
vals
[
i
]);
vComm
->
Recv
(
0
,
tmp
);
m_compOrder
[
keys
[
i
]]
=
tmp
;
}
keys
.
resize
(
bndSize
);
vals
.
resize
(
bndSize
);
vComm
->
Recv
(
0
,
keys
);
vComm
->
Recv
(
0
,
vals
);
for
(
int
i
=
0
;
i
<
keys
.
size
();
++
i
)
{
vector
<
unsigned
int
>
tmp
(
vals
[
i
]);
vComm
->
Recv
(
0
,
tmp
);
m_bndRegOrder
[
keys
[
i
]]
=
tmp
;
}
}
}
else
{
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment